Performance Modeling Engineer Processor, AI Accelerator, and SoC Architecture- Sr.Staff

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > DSP Architecture and Design

General Summary:

We are seeking an experienced Performance Modeling Engineer to drive architectural exploration, performance analysis, and system-level optimization for next-generation processors, AI accelerators, and SoC platforms. The ideal candidate will have deep expertise in processor architecture, memory systems, cache hierarchies, coherent interconnects, and transaction-level modeling (TLM).

In this role, you will work closely with architecture, RTL, verification, software, and system teams to develop high-fidelity performance models, evaluate architectural tradeoffs, and guide key design decisions from concept through silicon.

Minimum Qualifications:

•    Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 6+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 5+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

•    2+ years of experience with high-performance microprocessor design.

Responsibilities

·         Develop and maintain transaction-level and analytical performance models for processors, memory hierarchies, interconnects, and accelerators.

·         Create detailed models of:

o    Cache hierarchies

o    Coherent interconnects

o    Memory subsystems

o    DMA engines

o    Shared-memory multiprocessor (SMP) systems

·         Evaluate architectural tradeoffs involving:

o    Performance

o    Power

o    Area

o    Latency

o    Bandwidth

o    Scalability

·         Analyze workload behavior and identify system bottlenecks through simulation and modeling.

·         Drive architectural studies for next-generation multicore and cache-coherent systems.

·         Perform deep performance analysis of:

o    Branch prediction

o    Hardware prefetching

o    Speculative execution

o    Load/store architectures

o    Cache coherence protocols

o    Memory consistency models

·         Model and validate the behavior of multithreaded and multiprocessor workloads.

·         Collaborate with hardware and software teams to correlate performance models with RTL simulations, emulation results, and silicon data.

·         Present architectural recommendations and performance insights to engineering leadership.

Required Qualifications

·         BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field.

·         10+ years of industry experience in computer architecture, microarchitecture, or performance modeling.

·         Strong understanding of:

o    Processor architecture and microarchitecture

o    Cache and memory hierarchy design

o    Shared-memory multiprocessor (SMP) systems

o    Multicore scaling challenges

·         Experience developing:

o    Transaction-Level Models (TLM/SystemC)

o    Analytical performance models

o    Architectural simulators

·         Deep knowledge of cache behavior, including:

o    Capacity and conflict effects

o    Latency analysis

o    Prefetching techniques

o    Memory locality

o    Coherence interactions

·         Familiarity with modern cache coherence protocols such as:

o    ARM CHI

o    ACE

o    MESI/MOESI-based protocols

·         Strong understanding of:

o    Memory consistency models

o    Atomic operations

o    Synchronization mechanisms

o    Ordering semantics

·         Strong software development skills in C++, Python, or equivalent languages.

Preferred Qualifications

·         Experience modeling AI accelerators, CPUs, GPUs, or heterogeneous compute architectures.

·         Understanding of:

o    Network-on-Chip (NoC) architectures

o    Memory controllers

o    DDR and HBM memory systems

o    Virtualization technologies such as SR-IOV

·         Familiarity with formal verification methods for cache coherence and memory ordering.

·         Experience correlating pre-silicon performance models with silicon measurements and performance counters.

·         Knowledge of power-performance analysis and optimization techniques.

Key Technical Areas

·         Performance Modeling

·         Transaction-Level Modeling (TLM/SystemC)

·         Cache Modeling

·         Cache Coherence

·         ARM CHI

·         Processor Architecture

·         SMP Architectures

·         Multicore Systems

·         Memory Consistency Models

·         Branch Prediction

·         Hardware Prefetching

·         Speculative Execution

·         Interconnect and NoC Modeling

·         Memory System Architecture

·         AI Accelerator Architecture

·         Performance and Power Analysis

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Pay range and Other Compensation & Benefits:

$191,800.00 - $287,800.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.